3.5.1.23 Synthesize Hardware to FPGA
(Ask a Question)SmartHLS can run Libero to report FPGA resource and timing information. There are two options for Synthesize Hardware to FPGA:
- RTL synthesis only for resource results (faster runtime).
- RTL synthesis, place and route, for resource and timing results (slower runtime).
The following synthesis settings are used by SmartHLS:
- Enable Retiming
- Yes
- Map ROM components to
- RAM
- Additional options for Synplify
- set_option -maxfan 30
The following place and route settings are used by SmartHLS:
- High effort layout
- Yes
The Libero project will use block flow (-block_mode 1) to compile the generated IP core in isolation. For more details, see the<SMARTHLS_INSTALLATION_DIR>\SmartHLS\examples\synthesize_libero.tcl Tcl script that SmartHLS uses to run Libero synthesis, place and route.