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Libero SoC Design Suite Help Documentation v2024.2
Libero SoC Design Suite Help Documentation v2024.2
  1. Home
  2. 3 SmartHLS Compiler

    Information about SmartHLS Compiler

  3. 3.5 Working with SmartHLS

    Information and resources to help you work with SmartHLS.

  4. 3.5.1 User Guide
  5. 3.5.1.8 Automatic On-Chip Instrumentation

v2024.2

  • 1 What's New

    Information about what is new in Libero SoC Design Suite

  • 2 Download Help

    Information to help you download the Libero SoC Design Suite documentation

  • 3 SmartHLS Compiler

    Information about SmartHLS Compiler

    • 3.1 Overview

      Welcome to the User Manual of SmartHLS.

    • 3.2 Getting Started

      Information and resources to help you get started using SmartHLS as quickly as possible.

    • 3.3 Technical Support
    • 3.4 Quick Start Tutorial

      Learn how to use some of the major features and optimization techniques of SmartHLS.

    • 3.5 Working with SmartHLS

      Information and resources to help you work with SmartHLS.

      • 3.5.1 User Guide
        • 3.5.1.1 Introduction to High-Level Synthesis
        • 3.5.1.2 SmartHLS Overview
        • 3.5.1.3 SmartHLS SoC Flow
        • 3.5.1.4 SmartHLS Pragmas
        • 3.5.1.5 SmartHLS Constraints
        • 3.5.1.6 Specifying the Top-level Function
        • 3.5.1.7 Simulate HLS Hardware (SW/HW Co-Simulation)
        • 3.5.1.8 Automatic On-Chip Instrumentation
          • 3.5.1.8.1 Introduction
          • 3.5.1.8.2 Modes
          • 3.5.1.8.3 Instrumentation Flows
          • 3.5.1.8.4 Generated Files
        • 3.5.1.9 Loop Pipelining
        • 3.5.1.10 Loop Dependence
        • 3.5.1.11 Function Pipelining
        • 3.5.1.12 Data Flow Parallelism
        • 3.5.1.13 Multi-threading with SmartHLS Threads
        • 3.5.1.14 Supported HLS Thread APIs
        • 3.5.1.15 Data Flow Parallelism with SmartHLS Threads
        • 3.5.1.16 Memory Partitioning
        • 3.5.1.17 Struct Support
        • 3.5.1.18 Error Correction Code
        • 3.5.1.19 SmartHLS C/C++ Library
        • 3.5.1.20 Top-Level RTL Interface
        • 3.5.1.21 API Driver Functions for AXI4 Target
        • 3.5.1.22 Specifying a Custom Test Bench
        • 3.5.1.23 Synthesize Hardware to FPGA
        • 3.5.1.24 SoC Features
        • 3.5.1.25 Report Files
        • 3.5.1.26 Schedule Viewer
        • 3.5.1.27 Instantiating SmartHLS IP Core in Libero
        • 3.5.1.28 Hardware Integration of SmartHLS™ modules into SoC SmartDesign
        • 3.5.1.29 User-defined SmartDesign
        • 3.5.1.30 SmartHLS Output Files
        • 3.5.1.31 SmartHLS™ Command-Line Interface
        • 3.5.1.32 Software Macros
        • 3.5.1.33 HLS Makefile
      • 3.5.2 Optimization Guide

        Learn how to optimize the generated hardware through software code changes and SmartHLS pragmas/constraints.

      • 3.5.3 Hardware Architecture

        Describes the hardware architecture produced by SmartHLS.

    • 3.6 Additional References

      Information about the additional references to help you use SmartHLS.

    • 3.7 SmartHLS™ Examples

      Information about SmartHLS examples.

  • 4 Installation and Licensing

    Information about Libero SoC software installation and licensing

  • 5 Design Flow

    Information about Design Flow

  • 6 Block Flow

    Information about Block Flow

  • 7 SmartDesign

    Information about SmartDesign

  • 8 Netlist Viewer

    Information about Netlist Viewer

  • 9 I/O Editor

    Information about I/O Editor

  • 10 PDC Commands

    Information about PDC commands for all families

  • 11 Chip Planner

    Information about Chip Planner

  • 12 Timing Constraints Editor

    Information about Timing Constraints Editor

  • 13 SmartTime Static Timing Analyzer

    Information about SmartTime Static Timing Analyzer

  • 14 SmartPower

    Information about SmartPower

  • 15 Programming and Debugging

    Information about Programming and Debugging

  • 16 Macro Library

    Information about Macro Library for SmartFusion2, IGLOO2 and PolarFire

  • 17 Custom Flow

    Information about Custom Flow

  • 18 Design Separation Methodology

    Information about Design Separation Methodology

  • 19 Microchip Separation Verification Tool

    Information about Microchip Separation Verification Tool

  • 20 PolarFire SoC Microcontroller Subsystem (MSS)

    Information about PolarFire SoC Microcontroller Subsystem (MSS)

  • 21 Tcl Command Reference

    Information about Tcl Command Reference

  • 22 Additional Information

    Additional information about other Microchip products

  • 23 Technical Support
  • 24 About Microchip

    More information about Microchip

3.5.1.8 Automatic On-Chip Instrumentation

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