3.5.1.30 SmartHLS Output Files

After compiling software to hardware, SmartHLS produces multiple output files. This section will describe the location and purpose for each one.

Verilog Files

The generated hardware module(s) are produced in the sub-directory hls_output/rtl. By default, each top-level module, along with all its child modules, will be printed to a separate Verilog file (<Project Name>_<Top Level Name>.v). If it is desired to print all Verilog into a single file (<Project Name>.v), users can configure the SINGLE_HDL_OUTPUT_FILE parameter.

VHDL Wrapper Files

SmartHLS produces VHDL wrapper files which contain a top-level VHDL entity that wraps a corresponding Verilog top-level module. By default, there will be a single VHDL file for each Verilog top-level module (<Project Name>_<Top Level name>.vhd). If it is desired to print all VHDL into a single file (<Project Name>.vhd), users can configure the SINGLE_HDL_OUTPUT_FILE parameter.

Reports

Multiple report files are produced in the sub-directory hls_output/reports. For more information on these reports please see Report Files.

Scripts

SmartHLS produces multiple Tcl scripts in the sub-directory hls_outputs/scripts. These scripts can be passed to Libero to automate the process of integrating SmartHLS accelerators with user designs. There are four types of scripts produced:

  • create_hdl_plus_<top_level>_top.tcl: For each top-level function, SmartHLS generates a Tcl script that can be called by Libero to create an HDL+ component containing the accelerator module of that top-level function. The HDL+ core can then be instantiated in SmartDesign and connected to the rest of the user’s design.
  • create_hdl_plus.tcl: This script invokes creates HDL+ cores for all accelerators by sourcing each create_hdl_plus_<top_level>_top.tcl script.
  • hierarchy.tcl: This script can be invoked by ModelSim, and will automatically add relevant signals to the waveform viewer, used for debugging in simulation.
  • shls_integrate_accels.tcl: This script invokes the create_hdl_plus.tcl script and then connects the generated HDL+ modules to the SmartHLS™ Reference SoC. It can be used as a reference for how the user can integrate generated hardware in their own SmartDesign project.

For more information on using these scripts to integrate SmartHLS accelerators with existing designs, please see Hardware Integration of SmartHLS™ modules into SoC SmartDesign.

Accelerator Driver Code

SmartHLS produces C++ code that the can be used to control the generated hardware from an attached processor in an SoC design. This accelerator driver code can be found in the sub-directory hls_output/accelerator_drivers. In the header file in that directory, there is a set of user-callable functions that can be used to control each accelerator. For a description of the accelerator driver functions, see API Driver Functions for AXI4 Target.

Reference SoC Design

SmartHLS can optionally generate a reference SoC design inside the hls_output/soc directory, containing a RISCV processor and the generated accelerators. For more details on this reference design, please see SmartHLS™ Reference SoC.