3.5.1.18 Error Correction Code

Error Correction Code (ECC) protected memory uses error correction code bits to detect and correct data corruption which occurs in memory. RTG4™ and PolarFire® devices support single-bit (SB) error correction and double-bit (DB) error detection for the embedded memory blocks. For more details, please refer to the RTG4 Fabric User Guide and the PolarFire Family Fabric User Guide.

SmartHLS™ supports instantiating ECC memory using memory pragma parameter ecc(true|false) (see Error Correction Code in SmartHLS Pragmas Manual).

#pragma HLS memory impl variable(x) ecc(true)
int x[100];

When a variable is specified to use ECC, uses Libero® SoC's RAM block memory configurator to instantiate the memory blocks. Detailed configuration of the generated RAM block will be displayed in the summary report from SmartHLS. For example, the report below shows that variable x is generated as a LSRAM with Non-Pipelined ECC mode enabled.

+------------------------------------------------------------------------------------------------------------------+
| Local Memories                                                                                                   |
+------+-----------------------+---------------------------------+-------------+------------+-------+--------------+
| Name | Accessing Function(s) | Type                            | Size [Bits] | Data Width | Depth | Read Latency |
+------+-----------------------+---------------------------------+-------------+------------+-------+--------------+
| x    | fct                   | RAM (LSRAM - Non-Pipelined ECC) | 3200        | 32         | 100   | 1            |
+------+-----------------------+---------------------------------+-------------+------------+-------+--------------+
CAUTION: Unaligned read/write access to ECC RAM will lead to undefined behavior and is not supported by SmartHLS. ECC feature only works for full words read/write.