3.5.1.22 Specifying a Custom Test Bench

SmartHLS allows one to use a custom test bench to simulate the hardware generated by SmartHLS. When a top-level function other than main is specified by the user, there are two options for simulation:

A custom test bench can be specified to SmartHLS via the HLS Constraints window:

One must specify both the name of custom Verilog module as well as the name of the custom test bench file. It can also be specified directly in the config.tcl file as the following:

set_custom_test_bench_module "testBenchModuleName"
set_custom_test_bench_file "testBenchFileName.v" 

This constraint is also described in set_custom_test_bench_module and set_custom_test_bench_file.