3.5.1.28 Hardware Integration of SmartHLS™ modules into SoC SmartDesign

As described before in Instantiating SmartHLS IP Core in Libero, HDL+ cores can be created for each module generated by SmartHLS. However, there is still a need to connect those cores to the rest of the system.

SmartHLS simplifies hardware/software design partition and exploration by making it easy to add or remove functions (verilog/VHDL modules), or to split a large function into smaller ones to improve timing and modularity. However, this flexibility moves the focus to system-level integration because it produces a very dynamic address mapping and decoding while exploring options and architectures. It is often necessary to connect (or disconnect) a variable number of modules into a larger project including their corresponding reset, clock and AXI interface signals for each module.

Integration greatly depends on the overall system architecture and is usually performed manually by a system architect. However, under certain assumptions integration of all the generated SmartHLS cores can be done automatically.

On the hardware side, the automated integration process is performed by a Tcl script called hls_ouput/scripts/shls_integrate_accels.tcl, which performs the following steps:

  1. Call the create_hdl_plus.tcl script (as described in Instantiating SmartHLS IP Core in Libero)Create the HLS subsystem:
    1. Instantiate the HLS AXI Interconnect and configure the address decoding
    2. Connect the created HDL+ cores in step 1 to the HLS AXI interconnect
    3. Connect the reset and clock signals
    4. Connect the HLS AXI Interconnect to the upstream AXI interface

As mentioned in the SmartHLS Reference SoC, SmartHLS uses the Icicle Kit Reference Design featuring a PolarFire® SoC Microprocessor Sub-System (MSS) to which the generated SmartHLS IP modules are automatically attached to via AXI interconnects.