67.7.12 MIPI DPHY Characteristics
The SAM9X7 Series complies with the protocol and electrical specifications of the following standards:
- MIPI Alliance Specification for Display Serial Interface (DSI) Version 1.2
- MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2), Version 1.2
- MIPI Alliance Specification for D-PHY, Version 1.2
Symbol | Parameter | Conditions | Min | Max | Unit |
---|---|---|---|---|---|
VDDIN33 | Supply voltage range (VDDIN33)(1) | – | 3.0 | 3.60 | V |
IDDIN33 | Current consumption (VDDIN33)(2) |
HS mode, 4 lanes |
– | 30.0 | mA |
tSTART | Start-up time(3) | – | – | 60 | μs |
High-Speed Characteristics | |||||
VCMTXDC | Output common mode voltage(2) | – | 150 | 250 | mV |
VOD | Output differential voltage(2) | – | 140 | 270 | mV |
VOHHS | Output high voltage(2) | – | – | 360 | mV |
ZOS | Output impedance(3) | – | 40 | 62.5 | Ω |
DZOS | Output impedance mismatch(3) | – | – | 10 | % |
fDSICK | MIPI_CLKx output frequency(3) | – | 40 | 500 | MHz |
BRLANE | Bit rate per lane(3) | – | 80 | 1000 | Mbps |
Low-Power Characteristics | |||||
VOH | High-level output(3) | – | 1.10 | 1.30 | V |
VOL | Low-level output(3) | – | -50 | 50 | mV |
ZOLP | Output impedance(3) | – | 110 | – | Ω |
tRLP / tFLP | 15% to 85% rise time and fall time(3) | CL < 70 pF | – | 25 | ns |
Note:
- This MIPI DPHY must be powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
- Lane load impedance is 80 to 125 Ω.
- Simulation data
Symbol | Parameter | Conditions | Min | Max | Unit |
---|---|---|---|---|---|
VDDIN33 | Supply voltage range (VDDIN33)(1) | – | 3.0 | 3.60 | V |
IDDIN33 | Current consumption (VDDIN33) | HS mode, 4 lanes | – | 15.0 | mA |
tSTART | Start-up time(2) | – | – | 60 | μs |
VIN | Recommended input voltage range(2) | On MIPI_CLKx and MIPI_Dx | -50 | 1350 | mV |
ILEAK | Input leakage current(2) | On MIPI_CLKx and MIPI_Dx | -10 | 10 | µA |
High-Speed Characteristics | |||||
VCMRXDC | Input common mode voltage range(1) | – | 70 | 330 | mV |
VIDTH | Differential input high voltage threshold(2) | – | – | 70 | mV |
VIDTL | Differential input low voltage threshold(2) | – | -70 | – | mV |
VIHHS | Input high voltage(2) | – | – | 460 | mV |
VILHS | Input low voltage(2) | – | -40 |
─ |
mV |
ZID | Differential input impedance(2) | – | 80 | 125 | Ω |
fCSICK | MIPI_CLKx output frequency(2) | – | 40 | 500 | MHz |
BRLANE | Bit rate per lane(2) | – | 80 | 1000 | Mbps |
Low-Power Characteristics | |||||
VIH | Input high level(2) | – | 880 | – | mV |
VIL | Input low level(2) | – | – | 550 | mV |
VHYST | Input hysteresis(2) | – | 25 | – | mV |
VIHF | Input high fault threshold(2) | – | 450 | – | mV |
VILF | Input low fault threshold(2) | – | – | 200 | mV |
- This MIPI DPHY must be powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
- Simulation data