67.7.8 PLL Characteristics

Table 67-42. PLLA Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33)⁽¹⁾	–	3.0	3.60	V
V_DDCORE	Supply voltage range (VDDCORE)	–	1.04	1.21	V
I_DDIN33	Current consumption (VDDIN33)⁽²⁾	PLLACK = 1.6 GHz	–	2.0	mA
I_DDCORE	Current consumption (VDDCORE)⁽²⁾	PLLACK = 1.6 GHz	–	2.5	mA
t_START	Start-up time⁽²⁾	–	–	50	μs
f_IN	Input frequency range	–	20	50	MHz
f_COREPLLCK	COREPLLCK frequency range	–	800	1600	MHz
f_PLLACK	Output frequency range (PLLACK)	–	f_COREPLLCK/ 2		MHz

Note:

This PLL is powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
Simulation data

Table 67-43. UPLL Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33)⁽¹⁾	–	3.0	3.60	V
V_DDCORE	Supply voltage range (VDDCORE)	–	1.04	1.21	V
I_DDIN33	Current consumption (VDDIN33)⁽²⁾	–	–	2.4	mA
I_DDCORE	Current consumption (VDDCORE)⁽²⁾	–	–	2.8	mA
t_START	Start-up time⁽²⁾⁽³⁾	–	–	150	μs
f_IN	Input frequency range⁽⁴⁾⁽⁵⁾	–	20	50	MHz
f_COREPLLCK	COREPLLCK frequency range	–	600	960	MHz
f_OUT	Output frequency range⁽⁶⁾	–	f_COREPLLCK / 2		MHz

Note:

This PLL is powered by an internal dedicated voltage regulator, supplied from VDDIN33, that must be started by software before enabling this PLL. Refer to Clock Generator.
Simulation data
Covers the start-up time of the PLL and of its dedicated voltage regulator.
Only 24 or 48 MHz input frequencies are authorized to support USB-related features and in particular those of the bootloader program in ROM.
For optimal settings of UPLL, set the PMC_PLL_ACR as follows:

PMC_PLL_ACR=0x12023010 for f_IN=[20 MHz, 32 MHz]

PMC_PLL_ACR=0x1B023010 for f_IN=[32 MHz, 50 MHz]
The post divider is hardwired in a divide-by-2 configuration.

Table 67-44. LVDS PLL Characteristics
Symbol	Parameters	Conditions	Min	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33)⁽¹⁾	–	3.0	3.60	V
V_DDCORE	Supply voltage range (VDDCORE)	–	1.04	1.21	V
I_DDIN33	Current consumption (VDDIN33)⁽²⁾	–	–	2.8	mA
I_DDCORE	Current consumption (VDDCORE)⁽²⁾	–	–	3.5	mA
t_START	Start-up time⁽²⁾	–	–	100	μs
f_IN	Input frequency range⁽³⁾	–	20	50	MHz
f_COREPLLCK	COREPLLCK frequency range	–	600	1200	MHz
f_LVDSPLLCK	Output frequency range (LVDSPLLCK)	–	175	550	MHz
f_PIXCK	Pixel clock frequency⁽⁴⁾	–	f_COREPLLCK/7		MHz

Note:

This PLL is powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
Simulation data.
For optimal settings of LVDS PLL, set the PMC_PLL_ACR as follows:

PMC_PLL_ACR=0x12023010 for f_IN=[20 MHz, 32 MHz]

PMC_PLL_ACR=0x1B023010 for f_IN=[32 MHz, 50 MHz]
This is the pixel clock feeding the LCD Controller when using the LVDS Controller.

Table 67-45. AUDIO PLL Characteristics
Symbol	Parameters	Conditions	Min	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33) ⁽¹⁾	–	3.0	3.60	V
V_DDCORE	Supply voltage range (VDDCORE)	–	1.04	1.21	V
I_DDIN33	Current consumption (VDDIN33)⁽²⁾	–	–	2.8	mA
I_DDCORE	Current consumption (VDDCORE)⁽²⁾	–	–	3.45	mA
t_START	Start-up time⁽²⁾	–	–	100	μs
f_IN	Input frequency range⁽³⁾	–	20	50	MHz
f_COREPLLCK	COREPLLCK frequency range	–	600	1200	MHz
f_AUDIOPLLCK	AUDIOPLLCK frequency range	–	–	300	MHz
f_AUDIOCLK	AUDIOCLK Output frequency range⁽⁴⁾	–	–	50	MHz

Note:

This PLL is powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
Simulation data
For optimal settings of AUDIO PLL, set PMC_PLL_ACR as follows:

PMC_PLL_ACR=0x12023010 for f_IN = [20 MHz, 32 MHz]

PMC_PLL_ACR=0x1B023010 for f_IN = [32 MHz, 50 MHz]
AUDIOCLK corresponds to the AUDIOCLK pin.