67.7.11 LVDS PHY Characteristics
The SAM9X7 Series complies with the LVDS standard TIA/EIA-644 for protocol and electrical specifications.
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| VDDIN33 | Supply voltage range (VDDIN33)(1) | – | 3.0 | 3.60 | V |
| IDDIN33 | Current consumption (VDDIN33)(2)(3) | Pre-emphasis disabled | – | 30.0 | mA |
| Pre-emphasis enabled | – | 50.0 | mA | ||
| tSTART | Start-up time(2) | – | – | 50 | μs |
| VOD | Output differential voltage(2) | – | +/-250 | +/-450 | mV |
| VCM | Output common mode voltage | – | 1.06 | 1.44 | V |
| VOHS | Single-ended output level high(2) | – | 1.21 | 1.64 | V |
| VOLS | Single-ended output level low | – | 0.91 | 1.24 | V |
| fLVDSCK | LVDS_CLK1x output frequency(2) | – | 57 | 79 | MHz |
| BRLANE | Bit rate per lane(4) | – | 175 | 550 | Mbps |
Note:
- This LVDS PHY must be powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
- Simulation data
- Four-lane data stream, 0.4 Mbps/lane, 100 Ohms load
- Maximum LVDS PHY operating data rate. From a system point of view, the display resolution is limited to 1280x720.