8.3.5 I/O Pins
| Symbol | Description | Min. | Typ.✝ | Max. | Unit | Conditions |
|---|---|---|---|---|---|---|
| Input Low Voltage | ||||||
| VIL | I/O PINS: | |||||
| IO5:IO0 | — | — | 0.2×VDD | V | INLVL selecting ST(1) | |
| VBUS | — | — | 0.9 | V | INLVL selecting TTL(1) | |
| with I2C levels | — | — | 0.3×VDD | V | ||
| RESET pin | — | — | 0.2×VDD | V | ||
| Input High Voltage | ||||||
| VIH | I/O PINS | |||||
| IO5:IO0 | 0.8×VDD | — | — | V | INLVL selecting ST(1) | |
| VBUS | 1.2 | — | — | V | INLVL selecting TTL(1) | |
| with I2C levels | 0.7×VDD | — | — | V | ||
| RESET pin | 0.8 × VDD | — | — | V | ||
| Input Leakage Current(1) | ||||||
| IIL | I/O Pins | — | +/- 5 | +/- 125 | nA | GND ≤ VPIN ≤ VDD, pin at high-impedance, TA= 85°C |
| RESET pin(2) | — | +/- 50 | +/- 200 | nA | GND ≤ VPIN ≤ VDD, pin at high-impedance, TA= 85°C | |
| Pull-up Current | ||||||
| IPUR | — | 150 | 200 | μA | VDD = 3.3V, VPIN = GND | |
| Output Low Voltage | ||||||
| VOL | Standard I/O pins | — | — | 0.6 | V | IOL = 10 mA, VDD = 3.3V |
| Output High Voltage | ||||||
| VOH | Standard I/O pins | VDD-0.7 | — | — | V | IOH = 6 mA, VDD = 3.3V |
| I/O Rise Time | ||||||
| tSR | Rising | — | 22 | — | ns | |
| Falling | — | 16 | — | ns | ||
| Pin Capacitance | ||||||
| CIO | I/O Pins | — | 5 | — | pF | |
✝ Data in the “Typ.” column is specified at TA = 25°C and VDD = 3.3V, unless otherwise specified. These parameters are not tested and are provided for design guidance only.
- The negative current is defined as the current sourced by the pin.
- The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
USB Pins
| Symbol | Description | Min. | Typ.✝ | Max. | Unit | Conditions |
|---|---|---|---|---|---|---|
| Input Leakage Current | ||||||
| IILUD | Input leakage on USB data pins DM | — | +/- 5 | +/- 125 | nA | GND ≤ VPIN ≤ VDD, pin at high-impedance, TA= 85°C |
| Input leakage on USB data pins DP | — | +/- 5 | +/- 125 | nA | GND ≤ VPIN ≤ VDD, pin at high-impedance, TA= 85°C | |
| I/O Rise Time | ||||||
| DP Rising | — | 13 | — | ns | ||
| DM Rising | — | 13 | — | ns | ||
| DP Falling | — | 14 | — | ns | ||
| DM Falling | — | 14 | — | ns | ||
| Input Capacitance | ||||||
| CUD | Input capacitance on USB data pins DM | — | 15 | 100 | pF | Pin at high-impedance |
| Input capacitance on USB data pins DP | — | 15 | 100 | pF | Pin at high-impedance | |
✝ Data in the “Typ.” column is specified at TA = 25°C and VDD = 3.3V, unless otherwise specified. These parameters are not tested and are provided for design guidance only.
- The negative current is defined as the current sourced by the pin.
- The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
