8.3.5 I/O Pins

Table 8-7. General I/O Pins
SymbolDescriptionMin.Typ.✝ Max.UnitConditions
Input Low Voltage
VILI/O PINS:
IO5:IO00.2×VDDVINLVL selecting ST(1)
VBUS0.9VINLVL selecting TTL(1)
with I2C levels0.3×VDDV
RESET pin0.2×VDDV
Input High Voltage
VIHI/O PINS
IO5:IO00.8×VDDVINLVL selecting ST(1)
VBUS1.2VINLVL selecting TTL(1)
with I2C levels0.7×VDDV
RESET pin0.8 × VDDV
Input Leakage Current(1)
IILI/O Pins+/- 5+/- 125nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

RESET pin(2)+/- 50+/- 200nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

Pull-up Current
IPUR150200μAVDD = 3.3V, VPIN = GND
Output Low Voltage
VOLStandard I/O pins0.6VIOL = 10 mA, VDD = 3.3V
Output High Voltage
VOHStandard I/O pinsVDD-0.7VIOH = 6 mA, VDD = 3.3V
I/O Rise Time
tSRRising 22ns
Falling 16ns
Pin Capacitance
CIOI/O Pins5pF

Data in the “Typ.” column is specified at TA = 25°C and VDD = 3.3V, unless otherwise specified. These parameters are not tested and are provided for design guidance only.

Note:
  1. The negative current is defined as the current sourced by the pin.
  2. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.

USB Pins

Table 8-8. USB Pin Specifications
SymbolDescriptionMin.Typ.✝ Max.UnitConditions
Input Leakage Current
IILUDInput leakage on USB data pins DM+/- 5+/- 125nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

Input leakage on USB data pins DP+/- 5+/- 125nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

I/O Rise Time
DP Rising 13ns
DM Rising 13ns
DP Falling 14ns
DM Falling 14ns
Input Capacitance
CUDInput capacitance on USB data pins DM15100pFPin at high-impedance
Input capacitance on USB data pins DP15100pFPin at high-impedance

Data in the “Typ.” column is specified at TA = 25°C and VDD = 3.3V, unless otherwise specified. These parameters are not tested and are provided for design guidance only.

Note:
  1. The negative current is defined as the current sourced by the pin.
  2. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.