2.13.6 Analog Sigma-Delta Digital to Analog Converter (DAC)

Unless otherwise noted, sigma-delta DAC performance is specified at 25 °C with nominal power supply voltages, using the internal sigma-delta modulators with 16-bit inputs, HCLK = 100 MHz, modulator inputs updated at a 100 KHz rate, in voltage output mode with an external 160 pF capacitor to ground, after trimming and digital [pre-]compensation.

Table 2-99. Analog Sigma-Delta DAC
SpecificationTest ConditionsMin.Typ.Max.Units
Resolution8—24Bits
Output range—0 to 2.56—V
Current output mode—0 to 256—µA
Output Impedance61012KΩ
Current output mode10——MΩ
Output voltage complianceCurrent output mode—0–3.0—V
–40ºC to +100ºC0–2.7—0–3.4V
Gain errorVoltage output mode—0.3±2%
–40ºC to +100ºC—0.3±2%
–55ºC to +125ºC—0.3±6%
Current output mode—0.3±2%
–40ºC to +100ºC—0.3±2%
–55ºC to +125ºC—0.3±6%
Output referred offsetDACBYTE0 = h’00 (8-bit)—0.25±1mV
–40ºC to +100ºC—1±2.5mV
Current output mode—0.3±1µA
–40ºC to +100ºC—1±2.5µA
Integral non-linearityRMS deviation from BFSL—0.10.4% FS1
Differential non-linearity—0.050.4% FS1
Analog settling time—Refer to Analog Sigma-Delta Digital to Analog Converter (DAC)—µs
Power supply rejection ratioDC, full scale output3334dB
Sigma-delta DAC power supply current requirements (not including VAREFx)Input = 0, EN = 1
(operational mode)———
VCC33SDDx3040µA
VCC15A35µA
Input = Half scale, EN = 1
(operational mode)——
VCC33SDDx—160165µA
VCC15A—3335µA
Input = Full scale, EN = 1
(operational mode)————
VCC33SDDx—280285µA
VCC15A—7075µA
Note:
  1. FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more information.
Figure 2-55. Sigma-Delta DAC Setting Time