2.13.6 Analog Sigma-Delta Digital to Analog Converter (DAC)

Unless otherwise noted, sigma-delta DAC performance is specified at 25 °C with nominal power supply voltages, using the internal sigma-delta modulators with 16-bit inputs, HCLK = 100 MHz, modulator inputs updated at a 100 KHz rate, in voltage output mode with an external 160 pF capacitor to ground, after trimming and digital [pre-]compensation.

Table 2-99. Analog Sigma-Delta DAC
Specification Test Conditions Min. Typ. Max. Units
Resolution 8 24 Bits
Output range 0 to 2.56 V
Current output mode 0 to 256 µA
Output Impedance 6 10 12
Current output mode 10
Output voltage compliance Current output mode 0–3.0 V
–40ºC to +100ºC 0–2.7 0–3.4 V
Gain error Voltage output mode 0.3 ±2 %
–40ºC to +100ºC 0.3 ±2 %
–55ºC to +125ºC 0.3 ±6 %
Current output mode 0.3 ±2 %
–40ºC to +100ºC 0.3 ±2 %
–55ºC to +125ºC 0.3 ±6 %
Output referred offset DACBYTE0 = h’00 (8-bit) 0.25 ±1 mV
–40ºC to +100ºC 1 ±2.5 mV
Current output mode 0.3 ±1 µA
–40ºC to +100ºC 1 ±2.5 µA
Integral non-linearity RMS deviation from BFSL 0.1 0.4 % FS1
Differential non-linearity 0.05 0.4 % FS1
Analog settling time Refer to 2.13.6 Analog Sigma-Delta Digital to Analog Converter (DAC) µs
Power supply rejection ratio DC, full scale output 33 34 dB
Sigma-delta DAC power supply current requirements (not including VAREFx) Input = 0, EN = 1
(operational mode)
VCC33SDDx 30 40 µA
VCC15A 3 5 µA
Input = Half scale, EN = 1
(operational mode)
VCC33SDDx 160 165 µA
VCC15A 33 35 µA
Input = Full scale, EN = 1
(operational mode)
VCC33SDDx 280 285 µA
VCC15A 70 75 µA
Note:
  1. FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more information.
Figure 2-55. Sigma-Delta DAC Setting Time