24.4.4.1 SCL Generation and Timings

The peripheral bus clock is suitably divided to generate the desired value of SCL. Different timing registers are used to divide the peripheral bus clock and generate the SCL. Push-pull and open-drain speeds of operation are automatically achieved by the controller based on the programmed values in the timing registers.

The controller supports the following registers to include the user-provided timing requirements of the I³C protocol:

• SCL I³C Open Drain Timing Register (I3CxSCLODTIM)
• SCL I³C Push Pull Timing Register (I3CxPPTIM)
• SCL I²C Fast Mode Timing Register (I3CxI2CFMTIM)
• SCL I²C Fast Mode Plus Timing Register (I3CxI2CFMPTIM)
• SCL Extended Low Count Timing Register (I3CxSCLELCNT)
• Bus Free and Available Timing Register (I3CxBUSTIM)
• SDA Hold Delay Timing Register (I3CxSDAHLDTIM)
• SCL Extended Termination Low Count Timing Register (I3CxSCLETLCNT)

Count values need to programmed, which are calculated based on the required period and the peripheral clock.

Count = Required period/Peripheral clock period.

The required period can be:

• High time or low time for Open-Drain/Push-Pull mode
• Bus free time

Example of programming the timing register fields for I³C transfers with the given peripheral clock frequency::

The calculation of the I3CxSCLODTIM [ODLCNT], I3CxPPTIM [PPLCNT] and I3CxPPTIM[PPHCNT] fields, as explained in this section, is based on the following assumptions:

• Peripheral clock frequency = 128 MHz (7.8 ns period)
• I³C speed = Maximum SCL clock frequency (12.8 MHz)
• I³C Push-Pull SCL minimum low period = 33 ns
• I³C Push-Pull SCL minimum high period = 41 ns
• I³C Open-Drain SCL minimum low period = 200 ns
• I³C Open-Drain SCL maximum high period = 41 ns

PPLCNT = I³C Push-Pull SCL minimum low period/peripheral clock period = 33 ns/7.8 ns ~=5

PPHCNT = I³C Push-Pull SCL minimum high period/ peripheral clock period = 41 ns/7.8 ns ~=5

ODLCNT = I³C Open-Drain SCL minimum low period/ peripheral clock period = 200 ns/7.8 ns ~=25