24.4.4.6 Clock Stalling

The controller stalls the SCL clock during specific scenarios of non-HDR transfers. This is to accommodate intermittent system latencies during command pipelining, transmit data pre-fetching, response reading, and so on. The controller also provides additional knobs in the form of Start Thresholds and Buffer Thresholds to avoid clock stalling.

Clock stalling is a feature that helps avoid overrun and underrun errors in the case of SDR, notwithstanding all of the mentioned measures. The controller software receiving these errors is an indication of a larger issue in itself, and neither clock stalling by itself nor termination of transfers during clock stalling is the solution.

Table 24-14. Clock Stalling Conditions
Sl No.	Transfer Command	Previous Command Condition	Condition to Enter Clock Stalling
I³C/I²C Transfer, ACK/NACK Phase
1	Write Transfer Regular command	TOC bit is set to '0'.	TX-FIFO is empty.
2	Read Transfer Regular command	TOC bit is set to '0'.	RX-FIFO is full.
3	Follow-up Directed CCC command without payload (Immediate/Regular) (Not 1st Directed CCC command)	Previous Directed CCC command TOC bit is set to '0'.	CMD-QUEUE is empty.
4	Broadcast CCC Transfer with Regular command	TOC bit is set to '0'.	TX-FIFO is empty.
5	Directed CCC Write Transfer Regular command	TOC bit is set to '0'.	TX-FIFO is empty.
6	Directed CCC Read Transfer Regular command	TOC bit is set to '0'.	RX-FIFO is full.
7	Directed CCC command without Payload and ROC bit is set to '1'	TOC bit is set to '0'.	RESP-Queue is full.
8	Middle of I²C Write Transfer with Regular Transfer command	NA	TX-FIFO is empty.
9	Middle of I²C Write Transfer with Regular Transfer command	NA	RX-FIFO is full.
10	End of I²C Write Transfer Regular command (only controller terminates) and TOC bit set to '0'.	NA	Next command unavailable.
11	End of I²C Write Transfer Regular command (only controller terminates) and ROC bit is set to '1'.	NA	RESP-Queue is full.
12	End of I²C Read Transfer Regular command (either controller/target terminates) and TOC bit set to '0'.	NA	Next command unavailable.
13	End of I²C Read Transfer Regular command (only controller terminates) and ROC bit is set to '1'.	NA	RESP-Queue is full.
Write Data Transfer, Parity bit
14	Middle of Write Transfer Regular command	NA	TX-FIFO is empty.
15	End of Write Transfer Regular command (only controller terminates) and TOC bit set to '0'.	NA	Next command unavailable.
16	End of Write Transfer Regular command (only controller terminates) and ROC bit is set to '1'.	NA	RESP-Queue is full.
I3C Read Transfer, Transition bit
17	Middle of Read Transfer Regular command	NA	RX-FIFO is full.
18	End of Read Transfer Regular command (either controller/target terminates) and TOC bit set to '0'.	NA	Next command unavailable.
19	End of Read Transfer Regular command (only controller terminates) and ROC bit is set to '1'.	NA	RESP-Queue is full.
I3C IBI Transfer, Transition bit
20	Middle of IBI Read Data Transfer	NA	IBI-Data FIFO is full.
21	Middle of Auto Command Read Data Transfer	NA	IBI-Data FIFO is full.