20.18.1 PMC System Clock Enable Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
| Name: | PMC_SCER |
| Offset: | 0x0000 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CPKEY[3:0] | CPBMCK | ||||||||
| Access | W | W | W | W | W | ||||
| Reset | – | – | – | – | – | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PCK3 | PCK2 | PCK1 | PCK0 | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 23:20 – CPKEY[3:0] Clocks Enable Key
| Value | Name | Description |
|---|---|---|
| 0xA | PASSWD | This field must be written to 0xA to validate CPBMCK. |
Bit 17 – CPBMCK Main System Bus Clocks Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the Main System Bus Clocks if CPKEY = 0xA. |
Bits 8, 9, 10, 11 – PCKx Programmable Clock x Output Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the corresponding Programmable Clock output. |