17.4.2 Parity Check

Before writing to RAM, the control signals, address and write data are checked for correct parity. A parity error will cause one of the PARITY bits in the INTFLAGS register to be set.

For reads from RAM, parity on the read data is generated and output on the data bus.

The data bus has additional consistency checks, such as duplicated read/write/control strobes. Any failed consistency check is flagged as a parity error causing PARITYD, PARITYA or PARITYC in the INTFLAGS register to be set.