17.4.1 ECC Correction

The RAMCTRL’s ECC system provides SEC-DED capabilities to detect and correct single-bit and double-bit errors in the RAM.

The system protects against data written to or read from the wrong RAM address. The write address is coded into the ECC parity. If the ECC parity does not match that of the read address, an error is flagged in either the ECC1 or ECC2 bit of the INTFLAGS register.

An ECC error in the address part of the ECC check word is unrecoverable and cannot be corrected. Such an error indicates that data have been written to or read from the wrong address, as the ECC2 flag in the INTFLAGS register indicates. For more information, see the Resources Protected by ECC section.

The data bus signals are protected through parity and redundancy. This protects against errors on the data bus signals, e.g, data being read from or written to the wrong address or reads being changed to writes. A detected error on the data bus will lead to setting one of the PARITY bits in the INTFLAGS register. Note that an erroneous write will not be discarded; the addressed location will be affected by the write, and the contents of the addressed location must be considered corrupted. The application must appropriately recover from this error. Consider the entire RAM corrupt if the parity error is in the address, as there is no way of knowing which address was written to. For more information, see the Parity Check section.

The location of the failing bit is found in the SYNDROME register, and the failing address is available in the ADDR register.