16.3.5 Parity Check

Before accessing Flash and EEPROM, the address, write data, and control signals are checked for correct parity. A parity error will cause the memory access to be discarded and the PARITY bit in the INTFLAGSB register to be set.

For reads from Flash and EEPROM, parity on the read data is generated and transmitted on the data bus, allowing the bus initiator to verify the integrity of the read data.

The data bus has additional consistency checks, such as duplicated read/write strobes. Any failed consistency check is flagged as a parity error, i.e., the PARITY flag in the INTFLAGSB register is set, and the transfer is aborted.