16.3.7 Error Reporting

NVMCTRL has two bus interfaces, one for instruction fetch and one for data access (LPM/LD/ST/STM). ECC errors occurring in NVM memories are reported as follows:

Table 16-6. ECC Error Information
Memory	Which Information?	How to know?
Flash Fetch or NVM Data	Single- or double-bit	INTFLAGSB
	Word address	ADDR
	ECC Parity bits read from NVM	PARITY
	Failing bit in ECC word	SYNDROME

The NVM controller has several parallel logical interfaces: Flash write, Flash fetch, Flash data, EEPROM write and EEPROM read. A single ECC check circuit performs all ECC checking. Therefore, these checks will be serialized, and only one of the logical interfaces can generate an ECC error at any time. Whenever an ECC error is detected, the ADDR, PARITY and SYNDROME registers are frozen, and the appropriate flags in the INTFLAGSB register are set. The ADDR, PARITY and SYNDROME registers remain frozen as long as any ECC flags in the INTFLAGSB register is set.

An LD or LPM instruction in the address in ADDR is required to retrieve the failing word. Note that this word will already be ECC-corrected, at least in the case of a 1-bit error, so it may appear correct even though the flags indicate otherwise.