16.3.4 ECC Correction

The Error Correction Code (ECC) system provides Single Error Correction and Double Error Detection (SEC-DED) capabilities for the Flash and EEPROM. Single-bit errors can be detected and corrected. Double-bit errors cannot be corrected.

The system protects against data being written to or read from the wrong Flash or EEPROM address. The address is included in the ECC parity. Reading instructions or data from NVM is subject to an ECC check, and if the ECC parity does not match that of the read address, an error is flagged in the Interrupt Flags B (INTFLAGSB) register for Flash (FECC1 or FECC2 bits) or EEPROM (EECC1 or EECC2 bits).

An ECC error in the address part of the ECC check word is unrecoverable and cannot be corrected. Such an error indicates that data have been written to or read from the wrong address and will be reported by setting the FECC2 or EECC2 flag in the INTFLAGSB register, and a bus error will be returned to the bus master.

The location of the failing bit is found in the ECC Syndrome (SYNDROME) register, and the failing address is available in the Address (ADDR) register.

The data bus signals are protected through parity and redundancy which protects against errors on the data bus signals, for example, data being read from or written to the wrong address or reads being changed to writes. A detected error on the data bus will lead to the access being discarded and the corresponding PARITY bit in the INTFLAGSB register to be set. For more information, see the Parity Check section.