16.3.10 Interrupts
| Vector Name | Source Name | Condition | Dependency |
|---|---|---|---|
| NVMCTRL_ERROR | COMP | Mismatch between the duplicated ECC checkers | |
| EECC1 | Detected a 1-bit error in EEPROM | ||
| EECC2 | Detected a multi-bit error in EEPROM | ||
| FECC1 | Detected a 1-bit error in Flash | ||
| FECC2 | Detected a multi-bit error in Flash | ||
| PARITYA | Detected a parity error on the bus address signals | ||
| PARITYC | Detected a parity error on the bus control signals | ||
| PARITYD | Detected a parity error on the bus data signals | ||
| NVMCTRL_READY | EEREADY | EEPROM Ready |
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the peripheral (NVMCTRL.INTFLAGSA/B).
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral's Interrupt Control register (NVMCTRL.INTCTRLA).
Note: the INTFLAGSB register is routed to ERRCTRL, and are enabled or
disabled depending on the ERRCTRL configuration.
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag set. The interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGSA/B register(s) for details on clearing interrupt flags.