22.5.3 Timeout Value
| Name: | TIMEOUT |
| Offset: | 0x02 |
| Reset: | 0xFF |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TIMEOUT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 7:0 – TIMEOUT[7:0] Timeout Value
Determines the timeout value for triggering a machine check reset due to overstay in the CONFIG state and automatic transition from ALARM to FAULT state. The actual timeout value is TIMEOUT*4 clock cycles. A zero value disables the timeout mechanism.
The TIMEOUT counter is frozen when the CPU halts in debug mode as long as the device is NOT LOCKED
This register is only writable when the ERRCTRL is in the CONFIG state. A value written to the TIMEOUT register will be loaded into the timeout counter when the ERRCTRL enters the NORMAL state.