41.3.3.4 Output Formats
- An 8-bit ADC means 256 discrete levels (from 0 to 255)
- A 10-bit ADC means 1024 discrete levels (from 0 to 1023)
ADC result ϵ [0, 2N-1]
The output from an ADC conversion is given by the equations below:
Equation | Explanation |
---|---|
Single-Ended 8-bit conversion: | |
| |
Single-Ended 10-bit conversion: | |
|
- VIN is the input voltage
- VREF is the selected reference voltage
The ADC has two output registers, the Sample (ADCn.SAMPLE) and Result (ADCn.RESULT) registers. The 16-bit Sample register will always be updated with the latest ADC conversion output (one sample). In series and burst accumulation mode, samples are added in an internal sample accumulator, configured by the Sample Accumulation Number Select (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register. The accumulated result will automatically be transferred to the 16-bit Result register when all samples are completed. In single conversion modes, the Result register will be updated with the latest sample, identical to the Sample register.
The Left Adjust (LEFTADJ) bit in the Control F (ADCn.CTRLF) register enables the left-shift of the output data. If enabled, this will left shift the output from both the Result and Sample registers. Left adjusting the result will effectively scale the result such that however many samples are accumulated, the MSb of the result is always situated at the leftmost bit position in the Result register.
The data format for a sample is an unsigned number, where 0x000
represents zero, and 0x3FF
represents the largest number (full scale).
If the analog input is higher than the reference level of the ADC, the 10-bit ADC output
will be equal to the maximum value of 0x3FF
. Likewise, if the input is
below 0V, the ADC output will be 0x000
.
The following table shows the Result register output formats by mode of operation and left adjustment.
MODE(1) | LEFTADJ | RESULT[15:10] | RESULT[9:8] | RESULT[7:0] |
---|---|---|---|---|
0 | X(2) | 0x00 | Conversion[7:0] | |
1 | 0 | 0x00 | Conversion[9:0] | |
1 | Conversion[9:0] << 6 | |||
2 , 3 | 0 | Accumulation[15:0] | ||
2 , 3 | 1 | Accumulation[15:0] << (6 - SAMPNUM) |
- See section Operation Modes.
- Left adjust is not available in 8-bit mode.
The following table shows the Sample register output formats by mode of operation and left adjustment.
MODE(1) | LEFTADJ | SAMPLE[15:10] | SAMPLE[9:8] | SAMPLE[7:0] |
---|---|---|---|---|
0 | X | 0x00 | Conversion[7:0] | |
Other | 0 | 0x00 | Conversion[9:0] | |
1 | Conversion[9:0] << 6 |
- See section Operation Modes.