41.3.3.5 ADC Clock

The ADC clock (CLK_ADC) is down-scaled from the peripheral clock (CLK_PER), which can be configured by the Prescaler (PRESC) bit field in the Control B (ADCn.CTRLB) register. Refer to the ADC section of the Electrical Characteristics section for details on the minimum and maximum allowed values for the ADC clock (CLK_ADC) period.

Some of the internal timings in the ADC are independent of CLK_ADC. To ensure correct internal timing regardless of the ADC clock frequency, a 1 µs timebase, given in CLK_PER cycles, must be written in the Main Clock Timebase (MCLKTIMEBASE) register in the Clock Controller (CLKCTRL) peripheral. For more details, refer to the MCLKTIMEBASE register description in the CLKCTRL - Clock Controller section.