41.3.3.7 Conversion Timing
Some of the analog modules in the ADC are disabled between conversions and require time to initialize before conversion starts. Only the modules used by the current ADC configuration are enabled, and as the initializations run in parallel, the limiting factor is the module with the slowest initialization time.
By writing the Low Latency (LOWLAT) bit in the Control A (ADCn.CTRLA) register to
‘1
’, the latency of the ADC peripheral can be reduced. This will
keep the configured modules continuously enabled, effectively removing all
initialization time at the start of a conversion. The initialization time is still
needed when enabling the ADC for the first time and reconfiguring the ADC to use an
input or reference that requires initialization. The ADC Busy (ADCBUSY) bit in the
Status (ADCn.STATUS) register can be used to check if initialization is ongoing.
The following table shows the different initialization times needed by the analog modules.
Analog Module | LOWLAT | Initialization Time (µs) |
---|---|---|
ADC | 0 | 6 |
1 (1) | 0 | |
Settling of internal references | 0 | 40 |
1 (1) | 2(2) | |
Settling of internal references after changing from one internal reference voltage to another internal reference voltage | X | 20 |
Settling internal Temperature Sensor input | 0 | 40 |
1 (1) | 0 | |
Settling of internal Analog Comparator Reference DAC input | X | 20 |
- The LOWLAT timing values are valid between two conversions that both have the
LOWLAT bit written to ‘
1
’. - When changing from one internal reference voltage to another internal reference voltage. The full 40 μs delay will be used if changing from a non-internal reference to an internal reference.
The sampling period of the input to the ADC is configured through the Sample Duration (SAMPDUR) bit field in the Control E (ADCn.CTRLE) register as SAMPDUR + ½ CLK_ADC cycles.
If using an internal reference, the value of the SAMPDUR bit field in the Control E (ADCn.CTRLE) register must be ≥ (4 µs * fCLK_ADC) - 1.5.