38.6.5 Status A
| Name: | STATUSA |
| Offset: | 0x04 |
| Reset: | 0x04 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OK | BUSY | ERROR | |||||||
| Access | R | R | R | ||||||
| Reset | 1 | 0 | 0 |
Bit 2 – OK CRC OK
When this bit is read as ‘1’, the previous CRC has completed
successfully.
This bit is only valid when the BUSY bit is read as ‘0’.
Bit 1 – BUSY CRC Busy
When this bit is read as ‘1’, the CRCSCAN peripheral is busy.
BUSY will remain ‘1’ until completion of the entire scan, i.e.,
all addresses from the start to the end address have been scanned. As long as
the module is busy, the access to the control registers is limited.
Bit 0 – ERROR CRC Error
When this bit is read as ‘1’, the previous CRC completed with
failure, ERROR = (!BUSY & !OK).
This bit is connected as an NMI source and is set when a scan results in an
error, issuing an NMI request if the NMIEN bit in the Control A (CRCSCAN.CTRLA)
register is set to ‘1’.