The CRC result register represents the 32-bit result value. The low byte ([7:0],
suffix 0) is accessible at the original offset, and the n higher bytes can be
accessed at offset +n. The temporary registers do not buffer the CRC result
register. The Most Significant bit (MSb) of the CRC result is bit 31. If CRCSCAN
is in 16-bit CRC mode (the CRC Mode Select (CRCSEL) bit in the CRCSCAN.CTRLA
register is ‘0’), only bit field [15:0] is used, and bit field
[31:16] will read as ‘0’.
This register is the actual linear-feedback shift register (LFSR) used in the CRC
calculation. This register is reset by writing a ‘1’ to the
RESET bit in the CRCSCAN.CTRLA register. Such a reset must be performed between
each data block in MANUAL mode so that the CRC calculation on each block starts
with the correct initial value.
This register is only readable if the CRC Source (SRC) bit field configuration in
the CRCSCAN.CTRLA register is in MANUAL mode to prevent information leakage. Any
other configuration of the SRC bit field will cause all reads to return
‘0x0000_0000’.
If reading the reset value of the SFR in the CRC32 mode (CRCSEL=CRC32 in
CRCSCAN.CTRLA), the value read will be ‘0x0000_0000’ due to
post-processing of the read result.
