38.6.1 Control A
The bits in this register are not writable when the CRC is busy (the BUSY bit in the
Interrupt Flags (CRCSCAN.INTFLAGS) register is ‘1’), except for the
RESET bit, which is writable at any time.
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RESET | SRC[1:0] | PEREN | CRCSEL | NMIEN | ENABLE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – RESET Reset CRCSCAN
Writing this bit to ‘1’ resets the CRCSCAN peripheral. The
CRCSCAN Control and Status registers (CTRLA, INTFLAGS, INTCTRL, STATUSA) will be
cleared one clock cycle after the RESET bit is written to ‘1’.
The RESET bit is a strobe bit.
Bits 6:5 – SRC[1:0] CRC Source
The CRCSCAN can be enabled during internal Reset initialization to verify the Boot section before letting the CPU start (see the Fuses section).
| Value | Name | Description |
|---|---|---|
| 0x0 | BOOT | The CRC is performed on the boot section of the Flash |
| 0x1 | CODE | The CRC is performed on the application code section of the Flash |
| 0x2 | DATA | The CRC is performed on the application data section of the Flash |
| 0x3 | MANUAL | Manual mode, CRC is performed on data written to the Data (DATA) register |
Bit 4 – PEREN Enable Periodic Timer
This bit enables the periodic timer mechanism, which sets the Scan Period Done (PERIOD) flag in the Interrupt Flags (CRCSCAN.INTFLAGS) register every 32 scanned Flash words.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The periodic timer is disabled |
| 1 | ENABLE | The periodic timer is enabled |
Bit 3 – CRCSEL CRC Mode Select
This bit determines whether to use CRC32 or CRC16.
| Value | Name | Description |
|---|---|---|
| 0 | CRC16 | The CRC is performed using CRC16 |
| 1 | CRC32 | The CRC is performed using CRC32 |
Bit 1 – NMIEN Enable NMI Trigger
When this bit is written to ‘1’, a CRC error during the scan
will trigger an NMI.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The CRC error during scan will not trigger a NMI |
| 1 | ENABLE | The CRC CRC error during scan will trigger a NMI |
Bit 0 – ENABLE Enable CRCSCAN
Writing this bit
to ‘1’ enables the CRCSCAN peripheral with the current
settings. The ENABLE bit is cleared by hardware after a scan when the DONE bit
in the CRCSCAN.INTFLAGS register is set.
Writing this bit to
‘0’ has no effect.