29.5.2 Control B

Name: CTRLB
Offset: 0x01
Reset: 0x40

Bit 76543210 
 WDTMON[1:0]       
Access RR 
Reset 01 

Bits 7:6 – WDTMON[1:0] WDT Clock Monitor

This bit field controls the WDT Clock Monitor mechanism. This bit field is initialized from fuses by the system initialization process.
ValueNameDescription
0x0 OFF The WDT Clock Monitor is disabled
0x1 ON The WDT Clock Monitor is always on (Reset value)
0x2 SLEEP The WDT Clock Monitor is always on in normal and IDLE mode but automatically disabled when the MCU is in the POWERDOWN and STANDBY sleep modes
0x3 RESERVED Reserved