29.5.3 Status
| Name: | STATUS |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LOCK | CAUSE | CNTBUSY | SYNCBUSY | ||||||
| Access | R/W | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – LOCK Lock
Writing this bit to ‘1’ write-protects the CTRLA register.
It is only possible to write this bit to ‘1’. This
bit can be cleared in Debug mode only.
If the PERIOD value in the WDTCFG fuse is non-zero, the lock will automatically be set.
This bit is under CCP.
Bit 2 – CAUSE Reset Cause
The last WDT reset source. Reset only by POR/BOR.
| Value | Name | Description |
|---|---|---|
| 0x0 | OUTSIDE | Outside window. This also covers the case where one WDR is received while a prior one is processed. |
| 0x1 | TIMEOUT | Timeout |
Bit 1 – CNTBUSY CNT Synchronization Busy
This bit is set while synchronizing the counter value from the WDT clock domain to the system clock domain.
This bit is cleared by the system after the synchronization is finished.
CNT may become out-of-sync with the WDT counter when CLK_PER stops, e.g., in sleep mode.
This bit is not under CCP.
Bit 0 – SYNCBUSY Synchronization Busy
This bit is set after writing to the CTRLA register while synchronizing the data from the peripheral clock domain to the WDT clock domain.
This bit is cleared after finishing the synchronization.
This bit is not under CCP.