19.6.9 Priority Control 0


Bit	31	30	29	28	27	26	25	24
	RRLVLEN3			LVLPRI3[4:0]
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	RRLVLEN2			LVLPRI2[4:0]
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	RRLVLEN1			LVLPRI1[4:0]
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RRLVLEN0			LVLPRI0[4:0]
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0

Bits 7, 15, 23, 31 – RRLVLENn Level n Round-Robin Arbitration Enable

This bit controls which arbitration scheme is selected for DMA channels with priority level n. Refer to the Arbitration section for details.

Value	Description
0	Static arbitration scheme for channels with level n priority
1	Round-robin arbitration scheme for channels with level n priority

Bits 0:4, 8:12, 16:20, 24:28 – LVLPRIn Level n Channel Priority Number

When round-robin arbitration is enabled (PRICTRL0.RRLVLENn = 1) for priority level n, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level n.

When static arbitration is enabled (PRICTRL0.RRLVLENn = 0) for priority level n, and the value of this bit field is non-zero, it will not affect the static priority scheme.

This bit field is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLENn written to ‘0’).

Value	Name	Description
0x00	CHN0	DMA Channel 0
0x01	CHN1	DMA Channel 1
Other	—	Reserved

Name:	PRICTRL0
Offset:	0x14
Reset:	0x00000000
Property:	PAC Write-Protection