19.6.7 Quality of Service Control
| Name: | QOSCTRL |
| Offset: | 0x0E |
| Reset: | 0x2A |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DQOS[1:0] | FQOS[1:0] | WRBQOS[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 1 | 0 | 1 | 0 | |||
Bits 5:4 – DQOS[1:0] Data Transfer Quality of Service
This bit field controls the SRAM priority access during the data transfer operation. Refer to the SRAM Quality of Service section in the CPU and Architecture chapter for details.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
Bits 3:2 – FQOS[1:0] Fetch Quality of Service
This bit field controls the SRAM priority access during the fetch operation. Refer to the SRAM Quality of Service section in the CPU and Architecture chapter for details.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
Bits 1:0 – WRBQOS[1:0] Write-Back Quality of Service
This bit field controls the SRAM priority access during the write-back operation. Refer to the SRAM Quality of Service section in the CPU and Architecture chapter for details.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |