19.6.13 Pending Channels
| Name: | PENDCH |
| Offset: | 0x2C |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PENDCH1 | PENDCH0 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bits 0, 1 – PENDCHn Pending Channel n
This bit is cleared when trigger execution, as defined by the channel trigger action settings for DMA channel n, is initiated when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on DMA channel n.