19.6.1 Control

Name:	CTRL
Offset:	0x00
Reset:	0x0000
Property:	PAC Write-Protection, Enable-Protected


Bit	15	14	13	12	11	10	9	8
					LVLEN3	LVLEN2	LVLEN1	LVLEN0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
						CRCENABLE	DMAENABLE	SWRST
Access						R/W	R/W	R/W
Reset						0	0	0

Bits 8, 9, 10, 11 – LVLENn Priority Level n Enable

This bit controls whether requests with the corresponding level will be fed into the arbiter block. Refer to the Arbitration section for more details.

Note: This bit is not enable-protected.

Value	Description
0	Transfer requests for Priority level n will not be handled
1	Transfer requests for Priority level n will be handled

Bit 2 – CRCENABLE CRC Enable

This bit controls whether the CRC is enabled. Writing a ‘0’ to this bit will disable the CRC calculation when the CRC Status Busy (CRCSTATUS. CRCBUSY) flag is cleared. The bit is ‘0’ when the CRC is disabled.

Writing a ‘1’ to this bit will enable CRC calculation.

Note: This bit is not enable-protected.

Value	Description
0	The CRC calculation is disabled
1	The CRC calculation is enabled

Bit 1 – DMAENABLE DMA Enable

This bit controls whether the DMA is enabled. Writing a ‘0’ to this bit will disable the DMA module. If a ‘0’ is written during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing beat transfer is completed.

Note: This bit is not enable-protected.

Value	Description
0	The peripheral is disabled
1	The peripheral is enabled

Bit 0 – SWRST Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Writing a ‘1’ to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are ‘0’) resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error.

Value	Description
0	There is no Reset operation ongoing
1	A Reset operation is ongoing