19.6.10 Interrupt Pending

This bit is set when the channel selected by Channel ID field (ID) is pending.

This bit is otherwise cleared.

This bit is set when the channel selected by Channel ID field (ID) is busy.

This bit is otherwise cleared.

This bit is set when the channel selected by Channel ID field (ID) fetched an invalid descriptor.

This bit is otherwise cleared.

This bit is cleared by writing a ‘1’ to it.

This bit is set when the channel selected by Channel ID field (ID) has pending Suspend interrupt.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Channel ID (ID) Suspend interrupt flag.

This bit is cleared by writing a ‘1’ to it.

This bit is set when the channel selected by Channel ID field (ID) has a pending Transfer Complete interrupt.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag.

This bit is cleared by writing a ‘1’ to it.

This bit is set when the channel selected by Channel ID field (ID) has a pending Transfer Error interrupt.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Channel ID (ID) Transfer Error interrupt flag.

This bit field stores the lowest channel number with pending interrupts. The number is valid if the Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel (with a channel number lower than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources. When no pending channels interrupts are available, this bit field will always return a zero value when read.

When this bit field is written, indirect access to the corresponding Channel Interrupt Flag Status and Clear (CHINTFLAG) register is enabled.