19.6.4 CRC Checksum
The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The
register is reset to ‘0’ by default, but it is possible to reset all
bits to ‘1’ by writing to the CRCCHKSUM register directly. It is
possible to write this register only when the CRC module is disabled. If CRC-32 is
selected and the CRC Status Busy flag is cleared (i.e., CRC generation is completed or
aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.) and
complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status
Busy flag is set (i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual
content.
| Name: | CRCCHKSUM |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CRCCHKSUM[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CRCCHKSUM[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRCCHKSUM[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCCHKSUM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – CRCCHKSUM[31:0] CRC Checksum
This bit field stores the generated CRC result. The 16 MSbs are always read zero when CRC-16 is enabled.
