19.6.23 Channel Status

This register affects the DMA channel selected in the Channel ID (CHID.ID) register.
Name: CHSTATUS
Offset: 0x4F
Reset: 0x00
Property: –

Bit 76543210 
      FERRBUSYPEND 
Access RRR 
Reset 000 

Bit 2 – FERR Fetch Error

This bit is cleared when a Resume software command is executed by writing to the Command bit field in the Channel Control B (CHCTRLB.CMD) register.

This bit is set when an invalid descriptor is fetched.

Bit 1 – BUSY Busy

This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is disabled.

This bit is set when the DMA channel starts a DMA transfer.

Bit 0 – PEND Pending

This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.

This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received.