13.3.9 Clock Generator Divider
Register
Note: The FRC/BFRC variants of the CLKGEN2/3/4 do not implement
the clock divider; the divider ratio for the FRC CLKFEN is fixed at 1x. The
associated FRACDIV macro has an active register that contains the current value of
INTDIV[14:0] and FRACDIV[8:0]. The CLKxDIV contents are transferred into the FRACDIV
macro active registers after the associated DIVSWEN bit is set. The DIVSWEN bit is
cleared when the transfer is completed.
| Name: | CLK4DIV |
| Offset: | 0x3124 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | Reserved[31:24] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | Reserved[23:16] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | Reserved[15:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | Reserved[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – Reserved[31:0]
