9.4.10.7 IRT Status Register (IRTSTAT)
The IRT status register (IRTSTAT) is a 32-bit read/write register available for IRT firmware
status and is only reset on a cold Reset (POR or BOR). The IRTSTAT register usage is
defined by the IRT firmware. It can be used to store secure boot and other status
information across the device Resets. The IRTSTAT register is read-only when the PLCK
bit = ‘1’.
| FIRT[0] = OFF | FIRT[0] = ON | Notes | |
|---|---|---|---|
| IRT Region protection / access control | If configured, depends on the region's Flash protection configuration bits | Controlled by IRTCTRL.DONE and IRTCTRL.PLCK | FIRT[0] causes the IRTCTRL.DONE bit to make the IRT region inaccessible to the non-IRT regions, regardless of the region's individual protection bits. |
| i.e., assuming FIRT[0] is ON – if a region is configured as IRT and doesn't have any access blocked via the FPRxCTRL bits, once the IRT code sets the DONE bit and vectors to non-IRT space, PLCK will be set and the regions will become inaccessible. | |||
| IRTCTRL Write Access | Allowed | Write-protected | Once the IRT region is locked (PLCK = '1'), writes
to IRTCTRL will fail silently |
| IRTSTAT write access | Allowed | Write-protected | Once the IRT region is locked (PLCK = '1'), writes
to IRTSTAT will fail silently |
| Program flow from non-IRT regions to an IRT region | Allowed | Not allowed | Program flow control instructions from a non-IRT section to an IRT section will result in a bus error trap. |
| INTCON3.CPUBET will be set (CPU Instruction bus error) | |||
| Program memory reads from non-IRT regions to an IRT region | Allowed | Not allowed | Reads of an IRT section from a non-IRT section will result in a bus error trap. |
| INTCON3.XRAMBET will be set (X Data Bus error) | |||
| Program memory writes from non-IRT regions to an IRT region | Allowed | Not allowed | Writes to an IRT section from a non-IRT section will be blocked, and result in an NVM Security Access Violation error. NVMCON.WREC will reflect this. |
| If enabled, an NVM interrupt will also be generated due to the NVM operation resulting in an error. | |||
| No traps occur in this case. |