9.4.10.6 IRT Control Register (IRTCTRL)

The IRT control register, IRTCTRL, includes the EAA, DBG, IACT, DONE and PLCK bits. IRTCTRL is read-only except when the PLCK bit = ‘0’.

• The EAA bit controls debug entry when secure debug is enabled.
• The DBG bit controls debug access to the IRT partition when IRT and secure debug are enabled.
  • This bit is cleared by a cold reset (POR or BOR) and must be set by IRT firmware to enable IRT firmware debugging.
  • When DBG bit == ‘0’, there is no debug access. CPU breakpoints and debugger memory accesses are disabled. IRT partition access (PLCK == ‘0’) is only enabled during IRT execution.
  • When DBG bit == ‘1’, debug access to the IRT partition is enabled. CPU breakpoints and debug memory accesses are allowed during IRT execution. IRT partition access (PCLK == ‘0’) is enabled when the device resets into debug mode.
• The DONE bit is set by the IRT (or another root of trust firmware) upon completion of root of trust execution. The IRT partition is locked (PLCK == ‘1’) when the DONE bit is set, and there is a subsequent instruction fetch from a non-IRT region, including erroneous fetches due to access violations or uncorrectable bit errors.
• The PLCK bit is a read-only bit that indicates if the IRT partition is locked (access disabled, bit == ‘1’).
  • If PLCK == ‘1’, IRTCTRL and IRTSTAT are read-only.