13.3.6 Clock Generator Divider Register
Note: The FRC/BFRC variants of the CLKGEN2/3/4 do not implement
the clock divider; the divider ratio for the FRC CLKFEN is fixed at 1x. The
associated FRACDIV macro has an active register that contains the current value of
INTDIV[14:0] and FRACDIV[8:0]. The CLKxDIV contents are transferred into the FRACDIV
macro active registers after the associated DIVSWEN bit is set. The DIVSWEN bit is
cleared when the transfer is completed.
| Name: | CLKxDIV |
| Offset: | 0x311C, 0x3124, 0x312C, 0x3134, 0x313C, 0x3144, 0x314C, 0x3154, 0x315C, 0x3164, 0x316C, 0x3174, 0x317C, 0x3184 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| INTDIV[14:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| INTDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRACDIV[8:1] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FRACDIV[0] | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 30:16 – INTDIV[14:0] Integer Divider bits
Number of Source Clocks in each 1/2 period of the Divided Clock.
Period Ex:
Divided Clock Period = [Source Clock Period] * INT * 2
Frequency Ex:
111111111111111 = Clock Generator
Divided Clock = Source Clock divided by 65,534
(32,767 *2)
111111111111110 = Clock Generator Divided Clock
Clock = Source Clock divided by 65,532
(32,766 *2)
| Value | Description |
|---|---|
| 000000000000011 | Clock Generator Divided Clock = Source Clock divided by 6 (3*2) |
| 000000000000010 | Clock Generator Divided Clock = Source Clock divided by 4 (2*2) |
| 000000000000001 | Clock Generator Divided Clock = Source Clock divided by 2 (1*2) |
| 000000000000000 | Clock Generator Divided Clock = Source Clock (no divider) |
Bits 15:7 – FRACDIV[8:0] Fractional Divider bits
Note: When INTDIV[14:0] =
0, written values
of this bit are not valid.The number of source clock periods is added over 512 source clocks as equally as possible to each half period of the output clock.
Provides a fractional additive value for 1/2 period of the output clock.
| Value | Description |
|---|---|
| 111111110 | 510/512 (0.99609375) divisor added to Integer value |
| 111111111 | 511/512 (0.998046875) divisor added to Integer value |
| 100000000 | 256/512 (0.5000) divisor added to Integer value |
| 000000010 | 2/512 (0.390625) divisor added to integer value |
| 000000001 | 1/512 (0.001953125) divisor added to integer value |
| 000000000 | 0/512 (0.0) divisor added to integer value |