1.4.3 AXI4 Limitations
(Ask a Question)Unsupported AXI4 features in the PCIESS are:
- 8, 16, and 32 bits data bus widths.
- User-defined signals.
- Low-power interface.
- Exclusive accesses are not supported.
Unsupported AXI4 features in the PCIESS are:
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.