1.2.5 Extended CRC

The PCIESS optionally performs automatic ECRC to ensure data integrity by default is disabled. The PCIE_PEX_SPC2 bridge configuration register controls the ECRC settings. For information about Configuration registers, see respective PolarFire Device Register Map or PolarFire SoC Register Map.

ECRC is enabled when PCIE Specific Capabilities Settings Register PCIE_PEX_SPC Bit[31] is set to 1 to indicate Advanced Error Reporting (AER) is enabled. ECRC error generation and checking can further be individually disabled or enabled by PCIE_PEX_SPC2 Bit[1] and Bit[2] register .