1.3.2 Scatter-Gather DMA Descriptors
(Ask a Question)The following table lists the Scatter-Gather DMA Descriptors.
| Name | Byte Offset | R/W | Description |
|---|---|---|---|
| DESC_STATUS | 0x00 - 0x03 | RW | Enables dynamic monitoring of the SGDMA transfer (when 0th bit of DESC_CONTROL register is set) Bits [3:0]: Provides the status number of the DMA engine. This number is incremented, enabling the application to determine the last processed descriptor, which is key in streaming flow between asynchronous devices. Bits [7:4]: Bit 4: Indicates SG-DMA descriptor has been processed. Bit 5: Indicates an error occurred during the processing of the current SGDMA descriptor. Bit 6: Indicates an End of Packet (EOP) condition has been reported by the source of the SGDMA transfer. Bit 7: Reserved Bits [31:8]: Indicates the Processed Page Size, which is the actual written or read page size. |
| DESC_CONTROL | 0x04 - 0x07 | RO | DESC_CONTROL enables dynamic control of the SGDMA transfer. Bit [0]: Defines whether the DMA engine provides a status report by writing to DESC_STATUS when the current SGDMA descriptor has been processed. Bits [3:1]: Reserved Bits [7:4]: Defines when an interrupt must be issued. Bit 4: Indicates an IRQ is issued when this SGDMA descriptor has been processed. Bit 5: Indicates an IRQ is issued if an error occurs. Bit 6: Indicates an IRQ is issued if the source of the transfer reports an EOP condition. Bit 7: Reserved Bits [31:8]: Provides the page size in bytes, from 1 to 16 M bytes. |
| DESC_NEXT_ADDR[63:32] | 0x0C - 0x0F | RO | Indicates next descriptor address. This field must be aligned on a 32-byte boundary. |
| DESC_NEXT_ADDR[31:5] | 0x08 - 0x0B | RO | Indicates next descriptor address. |
| DESC_NEXT_RDY[4] | Indicates if the next SGDMA Descriptor is ready and fetch-able. | ||
| DESC_SE_COND[3:0] | Defines the Start and End conditions for SGDMA descriptor processing. Bit 0: Indicates end the DMA transfer after this SGDMA descriptor has been processed (equivalent to an End Of Chain). Bit 1: Indicates to abort this SGDMA descriptor processing if an error occurs. Bit 2: Reserved Bit 3: Indicates to start this SGDMA descriptor processing when the source of the transfer reports a SOP reception. | ||
| DESC_SRC_ADDR[31:0] | 0x10 - 0x13 | RO | Indicates the source address of the descriptors. It must be 32 byte aligned. |
| DESC_SRC_ADDR[63:32] | 0x14 - 0x17 | RO | |
| DESC_DEST_ADDR[31:0] | 0x18 - 0x1B | RO | Indicates the destination address of the descriptors. It must be 32 byte aligned. |
| DESC_DEST_ADDR[63:32] | 0x1C - 0x1F | RO |