1.3.1 DMA Transfers

Each PCIe controller supports the following built-in DMA features, enabling low-power and efficient data transfer to the FPGA fabric:

  • Eight outstanding read and write requests
  • Completion re-ordering support
  • Flexible SGDMA modes, including dynamic DMA control per descriptor
  • DMA engine that reports to the descriptor for easy software management
  • Fetches up to three descriptors to optimize throughput

The PCIESS has two fully-independent DMA engines (DMA0 and DMA1), which helps to deliver higher performance on both, write and read functions. Each DMA engine can be configured to function as direct DMA or SGDMA. The DMA engines can be configured using PCIESS registers. For more information about DMA registers, see respective PolarFire Device Register Map or PolarFire SoC Register Map.

In direct DMA transfer mode, the DMA start address is a pointer to a contiguous data buffer mapped in the PCI bus address space. Data is read from and written to the buffer sequentially.

For DMA0, source is fixed to PCIe IF and destination is configurable. DMA0 is used to transfer data from:

  • PCIe link (Host PC memory) to EP AXI (LSRAM/DDR in EP design).
  • PCIe link (Host PC memory) to PCIe link (Host PC memory).

For DMA1, source is fixed to AXI IF and destination is fixed to PCIe IF. DMA1 is used to transfer data from EP AXI (LSRAM/DDR in EP design) to PCIe link (Host PC memory).

Figure 1-3. Direct DMA Transfer

In SG transfer mode, the DMA source and/or destination start address is a pointer to a chained list of page descriptors. Each descriptor contains the address and size of a data block (page), and a pointer to the next descriptor block to enable circular buffers.

Figure 1-4. SGDMA Transfer

The implementation of SGDMA transfer is different in DMA0 and DMA1.

SGDMA Transfer in DMA0

Source and Destination addresses are set according to the Descriptor. DMA source is always PCIe link and destination can be configured as PCIe link or AXI Master.

Figure 1-5. DMA0 Descriptor
Note: For DMA0, addresses and length must be multiples of 4 bytes. Source and destination start addresses must be 32 byte aligned. For example, if the start address is 0xXX14 and the destination address can be 0xXX14, 0xXX34, 0xXX54 and so on.

SGDMA Transfer in DMA1

Source and destination addresses are set by two independent Scatter-Gather descriptors all DMA destination is always PCIe and source is AXI IF.

Figure 1-6. DMA1 Descriptor
Note: For DMA1, addresses and length must be multiple of 32 bytes. Source and destination start addresses must be 32 byte aligned.