16.4.3.7 Watchdog Reset

A Watchdog reset is entered when a Watchdog 0 or Watchdog 1 fault occurs and if the corresponding watchdog is configured to generate a reset (WDTx_MR.RPTHRST or WDTx_MR.PERIODRST). This reset lasts three MD_SLCK cycles.

A Watchdog reset can reset the circuit fully or partially:

• The PMC controller is reset if RSTC_MR.WDTPMCx=1. If the PMC is not reset, the clock configuration is maintained after the Watchdog reset.
• The NRST pin is asserted if WDTx_MR.WDNRSTDIS=0. The duration of the NRST pin assertion depends on the RSTC_MR.ERSTL value. However, the resulting low level on NRST does not result in a User reset.

The watchdog timer is always reset after a Watchdog reset, and the watchdog is enabled by default and with a period set to a maximum.

When WDTx_MR.WDRSTEN=0, the Watchdog fault has no impact on the RSTC.