16.4.3.1 General Reset

A General reset occurs when the VDD3V3 voltage is below the threshold of the VDD3V3 POR and the VBAT voltage is below the VBAT POR threshold (first power-up).

In Active mode, a General reset occurs if VBAT is selected as the voltage source of VDDBU and is below the VBAT POR threshold (erroneous voltage selection resulting in a loss of data in the backup domain).

The NRST line rises two cycles after the VDDCORE reset line, as ERSTL defaults at value 0x0.

The PMC reset is de-asserted once the NRST pin has been sampled as inactive.

The processor and peripheral reset lines are de-asserted once the Flash power-up sequence has ended.

Once all the reset signals are released, RSTC_SR.RSTTYP reports a General reset.

Figure 16-3. General Reset Timing Diagram

Table 16-1. General Reset Timings
Name	Value	Unit	Description
t_bupstup	16	MD_SLCK	Backup start-up time. VDD3V3 POR rising to backup area logic reset release
t_vrstup	8	MD_SLCK	Voltage regulator start-up time. Voltage regulator power on to VDDCORE POR assertion
t_core	7	MD_SLCK	VDDCORE POR to core area logic reset
t_nrstout	5	MD_SLCK	Core area logic reset to NRST pin release
t_nrstdbc	2	MD_SLCK	NRST pin debouncing time
t_pwrup	5	ms	Flash power-up time