16.4.3.6 CPU Clock Failure Detection Reset

The system embeds a CPU clock frequency monitor that is located in the PMC. It can be enabled by setting CKGR_MOR.BMCKRST.

The CPU Clock Failure Detection reset is done when the CPU frequency monitor detects a failure and RSTC_MR.CPUFEN=1. This reset lasts three MD_SLCK cycles.

When RSTC_MR.CPUFEN=0, the slow crystal oscillator fault has no impact on the RSTC.

During a CPU Clock Failure Detection reset, the processor reset and the peripheral reset are asserted. The NRST line is also asserted, depending on the value of RSTC_MR.ERSTL.

When the CPU clock failure generates a VDDCORE reset, PMC_SR.MCKMON is automatically cleared by the peripheral and core reset.

Figure 16-8. CPU Clock Failure Detection Reset Timing Diagram