16.4.3.8 Software Reset

The RSTC offers commands to assert the different reset signals. These commands are performed by writing the Control register (RSTC_CR) with the following bits at ‘1’:

• RSTC_CR.PROCRST and RSTC_CR.PERRST—Writing a ‘1’ to PROCRST and PERRST resets the processor, its peripherals and the Watchdog Timer, whereas the coprocessor and its peripherals are not reset, including the memory system. If RSTC_MR.SFTPMCRS=1, the PMC is reset. If RSTC_MR.SFTPMCRS=0, the PMC is not reset. PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously).
• RSTC_CR.EXTRST: Writing a ‘1’ to EXTRST asserts low the NRST pin during a time defined by the field RSTC_MR.ERSTL.

The reset of the coprocessor and its peripherals is managed by RSTC_MR.CPROCEN and RSTC_MR.CPEREN.

The Software reset is entered if at least one of these bits is written to ‘1’ by the software. All these commands can be performed independently or simultaneously. The Software reset lasts three MD_SLCK cycles.

The internal reset signals are asserted as soon as the register write is performed. This is detected on the Main System Bus Clock (MCK). They are released when the Software reset has ended, i.e., synchronously to MD_SLCK.

If EXTRST=1, the NRST is driven low depending on the configuration of RSTC_MR.ERSTL. However, the assertion of NRST pin does not lead to a User reset.

If RSTC_CR.PROCRST and RSTC_CR.PERRST=1, the RSTC reports the software status in RSTC_SR.RSTTYP. Other Software resets are not reported in RSTTYP.

As soon as a software operation is detected, RSTC_SR.SRCMP=1. SRCMP is cleared at the end of the Software reset. No other Software reset can be performed while SRCMP=1, and writing any value in RSTC_CR has no effect.