16.4.3.9 User Reset

The User reset is entered when a low level is detected on the NRST pin and RSTC_MR.URSTEN=1. If URSTASYNC=1, a falling edge of the NRST input signal immediately asserts internal reset lines. If URSTASYNC=0, the NRST input signal is resynchronized and internal reset lines are asserted once a falling edge has been detected on the resynchronized NRST input signal.

In case of a User reset, the processor, coprocessor and all peripheral resets are asserted.

The User reset is released when NRST rises, after a two-cycle resynchronization time and a two-cycle processor start-up. The processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, RSTC_SR.RSTTYP is loaded with the value 0x4, indicating a User reset.

The NRST manager ensures that the NRST line is asserted for a number of slow clock cycles configured in RSTC_MR.ERSTL. However, if NRST pin does not rise during the configured period, because it is driven low externally, the internal reset lines remain asserted until NRST rises.