16.4.3.5 32.768 kHz Crystal Oscillator Failure Detection Reset

The system embeds two slow crystal frequency monitors: one is implemented in the Power Management Controller (PMC) and located in the VDDCORE power domain. The second frequency monitor is located in the SUPC powered by VDDBU. The monitor embedded in the PMC can be enabled by setting CKGR_MOR.XT32KFME to ‘1’. The monitor located in the backup area is always enabled and monitors the slow crystal frequency even if the system is in Backup mode.

The slow crystal oscillator failure detection reset is done when one of the two frequency monitors detects a failure and RSTC_MR.BADXTRST=1. This reset signal lasts three slow clock cycles.

When RSTC_MR.BADXTRST=0, the 32.768 kHz crystal oscillator fault has no impact on the RSTC.

When RSTC_MR.SCKSW=1 and RSTC_MR.BADXTRST=0, the 32.768 kHz crystal oscillator fault leads to an automatic TD_SLCK source switching from slow crystal oscillator to slow RC oscillator.

If the slow crystal oscillator failure detection is enabled to perform a system reset, the processor reset and the peripheral reset are asserted. The NRST line is also asserted, depending on the value of RSTC_MR.ERSTL.

When the slow crystal oscillator failure generates a VDDCORE reset, PMC_SR.XT32KERR is automatically cleared by the peripheral and core reset.